SPT2210SCT 查看數據表（PDF） - Signal Processing Technologies

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SPT2210SCT

Y/C VIDEO ENCODER

Signal Processing Technologies 

COMMAND REGISTER DESCRIPTIONS

BACKGROUND CONTROL

(Address = 06H)

D1 D0

MSB

LSB

Table XV – Background Control Description Table

Address Bit #

06H 7-2

1

0

Function

Bit Setting /Description

Not used

Fix at 0

Half Y/C and 50% Color Enable.

0 Half Y/C and 50% Color

Input Y value is reduced by 50% and

Disable

C is replaced with CLUT15 Cb/Cr data

1 Half Y/C and 50% Color

Enable

Half Y/C Enable. Input Y/C value is

reduced by half.

0 Half Y/C Disable

1 Half Y/C Enable

Default

00H

ACCESSING THE COMMAND REGISTERS

Access to the command registers for read or write pur-

poses is performed in the following sequence. It requires

the correct setting of the control lines and setting the data

on the bidirectional 8-bit data bus.

Command Register Read and Write Operation

Address Setup:

Set CS_, RS low.

Set the data bus to the address required, then set

WR_ low.

Set WR_ high, then CS_ and RS high.

This completes the address write and points to the regis-

ter that may be read from or written to.

Register Read:

After completing address setup, Set CS_ low, RS

high.

Set RD_ low, this enables the data from the pointed-to

register onto the data bus.

Set RD_, CS_ and RS high.

This completes the register read operation; subsequent

reads from the same register may be performed, if the

address has not been changed.

Register Write:

After completing address setup, set CS_ low, RS

high.

Set the data required onto the data bus, then set WR_

low.

Set WR_, CS_ and RS high, then release data bus

input data.

This completes the register write operation; subsequent

writes to the same register may be performed, if the

address has not been changed.

SPT

SPT2210

14

8/22/00

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