SPT2210SCT 查看數據表（PDF） - Signal Processing Technologies

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SPT2210SCT

Y/C VIDEO ENCODER

Signal Processing Technologies 

Table II – Y/C Video Encoder Pin Functions

Signal Pin

Name Numbers I/O Function

Digital Video Inputs and Controls

YD7...0 1-8

I Luminance Digital Input

(YD0 = LSB) (TTL Level)

CD7...0 57-64

I Color Difference Digital Input

(CD0 = LSB) (TTL Level)

CBF

11

I Cr/Cb Sampling Order Control

(TTL Level)

BLANK_ 12

I External Blanking Control Signal

Input (TTL Level)

FIELD

16

I Field Indicator Signal (TTL Level)

V

13

I/O Vertical Synchronization Signal

Input (TTL Level)

H

14

I/O Horizontal Synchronization Signal

Input (TTL Level)

KEY

17

I Keying Signal Input (TTL Level)

GD3...0 18-21

I CLUT Ram Address (GD0 = LSB)

(TTL Level)

VRTENB 15

I Vertical Interpolation Enable

(TTL Level)

SUSPEND 43

I Suspend Mode Enable/Disable

Video Outputs

Y

C

VREF

53

O Luminance or Composite Video

Analog Signal Output (1 VP-P)

49

O Chrominance Video Analog Signal

Output (1 VP-P) (Includes burst)

46

I Internal D/A Reference Voltage

Input

VCS

47

I Internal D/A Output Signal

Amplitude Control Voltage

MPU Interface and Clock

D7...0 29-32,36-39 I/O Address/Data Bus (TTL Level)

CS_

22

I Chip Select (TTL Level)

RS

23

I Register Select (TTL Level)

RD_

24

I Read from Data Bus (TTL Level)

WR_

25

I Write to Data Bus (TTL Level)

RESET_ 26

I Reset Signal Input (TTL Level)

CLK

34

I System Clock Input (Pixel Clock)

TEST

42

I Test Mode Enable/Disable

Power Supply Connections

VDD 10,28,35,41,56 - +3.3 V Power Supply for Digital

Circuitry

AVDD

44,52

- +3.3 V Power Supply for Analog

Circuitry

GND 9,27,33,40,55 - Ground for Digital Circuitry

AGND 45,48,54 - Ground for Analog Circuitry

DESCRIPTION OF PIN FUNCTIONS

DIGITAL VIDEO INPUTS AND CONTROLS

YD7...0 Pins

The luminance signal digital data is input on YD7...0 (TTL

level). The input can be in either offset binary or two’s

complement format. The range of the input data is

bounded from 16 to 235. Any data less than 16 is con-

verted to 16 and data greater than 235 is converted to

235. The active pixels will be output after completion of

the back porch as shown in figure 2. YD7 is the MSB and

YD0 is the LSB.

CD7...0 Pins

The color difference digital data is input on CD7...0 (TTL

level). The input can be in either offset binary or two’s

complement format. The input range of the offset binary

mode is from 16 to 240, and the input range of the two’s

complement mode is from –112 to +112. Signal data is

bounded to these minimum and maximum limits.

As a means of dealing with abnormal data, color kill is

carried out when 00(H) of FF(H) is detected for two suc-

cessive clocks or more at CD7...0 (automatic color kill

mode). Color kill is immediately cancelled when data

other than 00(H) or FF(H) are entered.

The order of Cr and Cb is determined by the combination

of the CBF pin (described below) and the Cr/Cb inversion

bit, D2 (data bit 2), of the command register CR1. In nor-

mal setup mode (Cr/Cb inversion bit = 0 and CBF pin = 1)

and 4:2:2 format, the input is started with the Cb data

and, after that, Cr and Cb are repeated alternately. (Refer

to figure 1.)

In the 4:1:1 format only (with normal CBF setup) the first

and the second data positions in time are used, and the

third and fourth data are ignored (or not present). (Refer

to figure 1.) The first data is repeated again after the

fourth data. The active pixels are output after the back

porch as shown in figure 2. CD7 is the MSB and CD0 is

the LSB.

CBF Pin

This is the Cr/Cb control pin. It determines the sampling

order of Cr/Cb. When the command register CR1, data

bit 2, (Cr/Cb inversion) is low (clear), the CBF pin is input

as positive true logic. (See the Command Register De-

scriptions.) When CBF is high, the SPT2210 samples the

data as Cb after the leading edge of HSYNC_ and the

back porch has occurred. When CBF is low, the SPT2210

samples the data as Cr after the leading edge of

HSYNC_ and the back porch has occurred.

When the command register CR1, data bit 2, (Cr/Cb In-

version) is high (set), the CBF pin is input as negative

logic. (See the Command Register Descriptions.) In this

mode the CBF pin is read as inverted.

SPT

SPT2210

3

8/22/00

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