SPT2210SCT 查看數據表（PDF） - Signal Processing Technologies

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SPT2210SCT

Y/C VIDEO ENCODER

Signal Processing Technologies 

RS_ Pin

This is the register select input pin (TTL level). The D7...0

pins operate as either address or data registers (except

when operating as external setting pins). The RS_ pin

determines the mode in which D7...0 will operate. When

RS_ is low the D7...0 bus is switched to the address bus

mode, and when it is high the bus is switched to the data

bus mode. The RS_ pin is also used as an external pin in

the external pin mode. Refer to the External Setting Pin

Descriptions section for more details.

RD_ Pin

This is the read enable input pin (TTL level). The data on

D7...0 is read out of the SPT2210 on the leading edge of

a high-to-low transition of RD_. If RS_ is high, the data is

read from the internal register specified by the last ad-

dress write. If RS_ is low, the current address value is

read from the address register. The RD_ pin is also used

in enabling the external pin mode. Refer to the External

Setting Pin Descriptions section for more details.

WR_ Pin

This is the write enable input pin (TTL level). The data on

D7...0 is written into the address or command register on

the leading edge of a high-to-low transition of RD_. If RS_

is high, the data is written into the internal command reg-

ister specified by the last address write. If RS_ is low, the

data is written into the address register. The WR_ pin is

also used in enabling the external pin mode. Refer to the

External Setting Pin Descriptions section for more

details.

Reset Pin

This is the reset input pin (TTL level). The reset input is

sampled on the leading edge of the system clock (CLK).

The SPT2210 is initialized by holding the RESET_ pin

low for a minimum of five clock cycles. The SPT2210 will

come out of reset five clock cycles after the RESET_ pin

has been brought back high.

CLK Pin

This is the system clock input pin (TTL level). The

YD7...0, CD7...0, GD3...0, BLANK_, V, H, Field and KEY

pins are all sampled on the rising edge of the CLK signal.

Additionally, when an asynchronous access from the

MPU is processed, the access is synchronized with this

clock and then the processing is carried out.

When the clock is switched over to another operating

frequency (i.e., changing video modes), the SPT2210

should be reset once to ensure proper operation. In this

case, the command registers will need to be set again.

VDD Pins

These are the +3.3 V power supply pins for the digital

circuitry.

AVDD Pins

These are the +3.3 V power supply pins for the analog

circuitry. VDD and AVDD are completely independent

of each other. Be sure to keep the following operating

condition:

| VDD – AVDD | ≤ 0.5 V.

GND Pins

These are the ground pins for the digital circuitry.

AGND Pins

These are the ground pins for the analog circuitry. Since

GND and AGND are completely independent of each

other, it is necessary to keep them at the same electric

potential by externally tying them together through a

ferrite bead.

Internal Pullup and Pulldown Resistors

The following pins are either pulled up or down with an

internal resistor of approximately 100 kΩ:

Pins with internal pulldown: CD7...0, YD7...0, GD3...0,

KEY, VRTENB, TEST, SUSPEND.

Pins with internal pullup: RESET_, BLANK_, V, H, CS_,

RD_, WR_, D7...0, CBF, RS, CLK.

SPT

SPT2210

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8/22/00

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