DS1743W-120 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
DS1743W-120 Datasheet PDF : 17 Pages
| |||
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
DATA
ADDRESS
B7
B6
B5
B4
B3
1FFF
10 Year
1FFE
X
X
X
10
Month
1FFD
X
X
10 Date
1FFC
BF FT
X
X
X
1FFB
X
X
10 Hour
1FFA
X
10 Minutes
1FF9
OSC
10 Seconds
1FF8
W
R
10 Century
B2
B1 B0
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
OSC = STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = SEE NOTE BELOW
BF = BATTERY FLAG
Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.
FUNCTION
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
RANGE
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–39
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in
the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable,
providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states
are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access
time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are
activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are
changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but
will then go indeterminate until the next address access.
7 of 17
Share Link: 