FT232BM(2004) 查看數據表（PDF） - Future Technology
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FT232BM Datasheet PDF : 54 Pages
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FT2232C Dual USB UART / FIFO I.C.
• 6MHz Oscillator
and receive registers. When configured as a
The 6MHz Oscillator cell generates a 6MHz
UART it performs asynchronous 7 / 8 bit Parallel
reference clock input to the x8 Clock multiplier from
to Serial and Serial to Parallel conversion of the
an external 6MHz crystal or ceramic resonator.
data on the RS232 (RS422 and RS485) interface.
Control signals supported by UART mode include
• x8 Clock Multiplier
RTS, CTS, DSR , DTR, DCD and RI. There
The x8 Clock Multiplier takes the 6MHz input
are also transmitter enable control signal pins
from the Oscillator cell and generates a 48MHz
(TXDEN) provided to assist with interfacing to
reference clock for the USB DPPL and the Baud
RS485 transceivers. RTS/CTS, DSR/DTR and
Rate Generator blocks.
Xon/Xoff handshaking options are also supported.
Handshaking, where required, is handled in
• Serial Interface Engine (SIE)
hardware to ensure fast response times. The
The Serial Interface Engine (SIE) block performs
UART’s also supports the RS232 BREAK setting
the Parallel to Serial and Serial to Parallel
and detection conditions.
conversion of the USB data. In accordance to the
USB 2.0 specification, it performs bit stuffing / un- • Baud Rate Generator
stuffing and CRC5 / CRC16 generation / checking
The Baud Rate Generator provides a x16 clock
on the USB data stream.
input to the UART’s from the 48MHz reference
clock and consists of a 14 bit prescaler and 3
• USB Protocol Engine
register bits which provide fine tuning of the baud
The USB Protocol Engine manages the data
rate (used to divide by a number plus a fraction).
stream from the device USB control endpoint. It
This determines the Baud Rate of the UART which
handles the low level USB protocol (Chapter 9)
is programmable from 183 baud to 3 million baud.
requests generated by the USB host controller
and the commands for controlling the functional
• RESET Generator
parameters of the UART / FIFO controller blocks.
The Reset Generator Cell provides a reliable
power-on reset to the device internal circuitry
• Dual Port TX Buffers (128 bytes)
on power up. An additional RESET# input and
Data from the USB data out endpoint is stored
RSTOUT# output are provided to allow other
in the Dual Port TX buffer and removed from the
devices to reset the FT2232C, or the FT2232C
buffer to the transmit register under control of the
to reset other devices respectively. During reset,
UART FIFO controller.
RSTOUT# is driven low, otherwise it drives out
at the 3.3V provided by the onboard regulator.
• Dual Port RX Buffers (384 bytes)
RSTOUT# can be used to control the 1.5K
Data from the UART / FIFO controller receive
pull-up on USBDP directly where delayed USB
register is stored in the Dual Port RX buffer prior
enumeration is required. It can also be used to
to being removed by the SIE on a USB request for
reset other devices. RSTOUT# will stay high-
data from the device data in endpoint.
impedance for approximately 5ms after VCC
has risen above 3.5V AND the device oscillator is
• Multi-Purpose UART / FIFO Controllers
running AND RESET# is high. RESET# should
The Multi-purpose UART / FIFO controllers handle
be tied to VCC unless it is a requirement to reset
the transfer of data between the Dual Port RX
the device from external logic or an external reset
and TX buffers and the UART / FIFO transmit
generator I.C.
DS2232C Version 1.2
© Future Technology Devices International Ltd. 2004
Page 7 of 54
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