EP9132 查看數據表（PDF） - Unspecified
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EP9132 Datasheet PDF : 26 Pages
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2.3 Pin Description
User Guide — EP9132_UG V0.1
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
NAME
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
A2, A1, A0
NAME
EXT_RSTb
V_OUT
reserved
NAME
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
RXC-
RXC+
EXT_RES
NAME
TX00-
TX00+
TX10-
TX10+
TX20-
TX20+
TXC0-
TXC0+
HTPLG0
Table 2-1 IIC Pins
IN /
OUT
IN
IO
OUT
IO
IN
IO
IN
DESCRIPTION
IIC SCL signal for receiver port DDC
IIC SDA signal for receiver port DDC (open drain)
IIC SCL signal for EE interface (open drain)
IIC SDA signal for EE interface (open drain)
IIC SCL signal for internal registers access
IIC SDA signal for internal registers access (open drain)
Determine the lowest 3-bit of the IIC addrress for IIC Port 3 (SCL3/SDA3)
Table 2-2 Misc. Pins
IN /
OUT
IN
OUT
IN
DESCRIPTION
External Reset (Active LOW). A HIGH level indicates normal operation and a
LOW level causes all the logic on the chip to be reset.
Polarity corrected vertical sync pulse (active high) derived from receiver
input
Must be tied LOW for normal operation.
Table 2-3 Receiver Pins
IN /
OUT
DESCRIPTION
Differential Data Input Pairs for receiver port
Analog
Differential Clock Input Pairs for receiver port
Analog DVI/HDMI External Termination Resistor
Table 2-4 Transmitter Pins
IN /
OUT
DESCRIPTION
Differential Data Output Pairs for transmitter port 0
Analog
Differential Clock Output Pairs for transmitter port 0
Hot Plug Input
IN This pin is used to monitor the "HOT PLUG" signal for tansmitter port 0. Note:
This input is only 3.3V tolerant and has no internal debouncer circuit.
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