AD9608 查看數據表（PDF） - Analog Devices
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AD9608 Datasheet PDF : 40 Pages
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AD9608
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS/SYNC)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
Temp Min
Typ
Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.3
3.6
Full
AGND − 0.3
AVDD + 0.2
Full
0.9
1.4
Full
−10
+10
Full
−10
+10
Full
4
Full
8
10
12
Full
1.22
Full
0
Full
−10
Full
40
Full
26
Full
2
DRVDD + 0.2
0.6
+10
132
Full
1.22
Full
0
Full
−92
Full
−10
Full
26
Full
2
DRVDD + 0.2
0.6
−135
+10
Full
1.22
Full
0
Full
−10
Full
38
Full
26
Full
5
DRVDD + 0.2
0.6
+10
128
Full
1.22
Full
0
Full
−90
Full
−10
Full
26
Full
5
DRVDD + 0.2
0.6
−134
+10
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
Full
1.79
Full
1.75
Full
Full
V
V
0.2
V
0.05
V
Rev. 0 | Page 6 of 40
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