AD9911 查看數據表（PDF） - Analog Devices
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AD9911 Datasheet PDF : 41 Pages
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AD9911
Data Sheet
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK
multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
Min
Typ Max
Unit
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier Bypassed
1
500
MHz
REF_CLK Multiplier Enabled
10
125
MHz
Internal VCO Output Frequency Range
255
VCO Gain Bit Set1
500
MHz
Internal VCO Output Frequency Range
100
VCO Gain Bit Cleared
160
MHz
Crystal REF_CLK Source Range
20
30
MHz
Input Power Sensitivity
−5
+3
dBm
Input Voltage Bias Level
1.15
V
Input Capacitance
2
pF
Input Impedance
1500
Ω
Duty Cycle with REF_CLK Multiplier Bypassed 45
55
%
Duty Cycle with REF_CLK Multiplier Enabled 35
65
%
CLK Mode Select (Pin 24) Logic 1 V
1.25
1.8
V
CLK Mode Select (Pin 24) Logic 0 V
0.5
V
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
10
mA
Gain Error
−10
+10
%FS
Output Current Offset
1
25
µA
Differential Nonlinearity
±0.5
LSB
Integral Nonlinearity
±1.0
LSB
Output Capacitance
3
pF
Voltage Compliance Range
AVDD –
0.50
AVDD + V
0.50
WIDEBAND SFDR
1 MHz to 20 MHz Analog Output
20 MHz to 60 MHz Analog Output
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 t MHz to 200 MHz Analog Output
WIDEBAND SFDR Improvement
Spur Reduction Enabled
−65
dBc
−62
dBc
−59
dBc
−56
dBc
−53
dBc
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 MHz to 200 MHz Analog Output
8
dBc
15
dBc
12
dBc
Test Conditions/Comments
Measured at the pin (single-ended)
1.8 V digital input logic
1.8 V digital input logic
Must be referenced to AVDD
10 mA is set by RSET = 1.91 kΩ
The frequency range for wideband SFDR is
defined as dc to Nyquist
Programs devices on an individual basis to
enable spur reduction. See the
SpurKiller/Multitone Mode section.
Rev. A | Page 4 of 41
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