ADCMP605BCPZ-WP(Rev0) 查看數據表（PDF） - Analog Devices

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ADCMP605BCPZ-WP
(Rev.:Rev0)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADCMP604/ADCMP605

Q1

6Q

ADCMP604

VEE 2 TOP VIEW 5 VCCI/VCCO

(Not to Scale)

VP 3

4 VN

Figure 3. ADCMP604 Pin Configuration

VCCO 1

VCCI 2

VEE 3

PIN 1

INDICATOR

ADCMP605

TOP VIEW

(Not to Scale)

9 VEE

8 LE/HYS

7 SDN

Figure 4. ADCMP605 Pin Configuration

Table 5. ADCMP604 (SC70-6) Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater

than the analog voltage at the inverting input, VN.

2

VEE

Negative Supply Voltage.

3

VP

Noninverting Analog Input.

4

VN

Inverting Analog Input.

5

VCCI/VCCO

Input Section Supply/Output Section Supply. VCCI and VCCO shared pin.

6

Q

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than

the analog voltage at the inverting input, VN.

Table 6. ADCMP605 (LFCSP-12) Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCCO

Output Section Supply.

2

VCCI

Input Section Supply.

3

VEE

Negative Supply Voltage.

4

VP

Noninverting Analog Input.

5

VEE

Negative Supply Voltage.

6

VN

Inverting Analog Input.

7

SDN

Shutdown. Drive this pin low to shut down the device.

8

LE/HYS

Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.

9

VEE

Negative Supply Voltage.

10

Q

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the

analog voltage at the inverting input, VN, if the comparator is in compare mode.

11

VEE

Negative Supply Voltage.

12

Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than

the analog voltage at the inverting input, VN, if the comparator is in compare mode.

Heat Sink

VEE

Paddle

The metallic back surface of the package is electrically connected to VEE. It can be left floating because

Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the

application board if improved thermal and/or mechanical stability is desired.

Rev. 0 | Page 7 of 16

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