82801HB 查看數據表（PDF） - Unspecified
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82801HB Datasheet PDF : 890 Pages
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5.27
5.28
Feature Capability Mechanism ........................................................................... 251
Serial POST Codes Over GPIO............................................................................ 252
5.28.1 Theory of operation............................................................................... 252
5.28.2 Serial Message Format .......................................................................... 253
6 Register and Memory Mapping ............................................................................... 255
6.1 PCI Devices and Functions ................................................................................ 255
6.2 PCI Configuration Map ...................................................................................... 257
6.3 I/O Map.......................................................................................................... 257
6.3.1 Fixed I/O Address Ranges ...................................................................... 257
6.3.2 Variable I/O Decode Ranges ................................................................... 260
6.4 Memory Map ................................................................................................... 261
6.4.1 Boot-Block Update Scheme .................................................................... 263
7 Chipset Configuration Registers ............................................................................. 265
7.1 Chipset Configuration Registers (Memory Space) ................................................. 265
7.1.1 VCH—Virtual Channel Capability Header Register ...................................... 268
7.1.2 VCAP1—Virtual Channel Capability #1 Register ......................................... 268
7.1.3 VCAP2—Virtual Channel Capability #2 Register ......................................... 268
7.1.4 PVC—Port Virtual Channel Control Register............................................... 269
7.1.5 PVS—Port Virtual Channel Status Register................................................ 269
7.1.6 V0CAP—Virtual Channel 0 Resource Capability Register.............................. 269
7.1.7 V0CTL—Virtual Channel 0 Resource Control Register ................................. 270
7.1.8 V0STS—Virtual Channel 0 Resource Status Register .................................. 270
7.1.9 V1CAP—Virtual Channel 1 Resource Capability Register.............................. 271
7.1.10 V1CTL—Virtual Channel 1 Resource Control Register ................................. 271
7.1.11 V1STS—Virtual Channel 1 Resource Status Register .................................. 272
7.1.12 PAT—Port Arbitration Table .................................................................... 272
7.1.13 CIR1—Chipset Initialization Register 1 ..................................................... 272
7.1.14 RCTCL—Root Complex Topology Capabilities List Register .......................... 273
7.1.15 ESD—Element Self Description Register ................................................... 273
7.1.16 ULD—Upstream Link Descriptor Register .................................................. 273
7.1.17 ULBA—Upstream Link Base Address Register ............................................ 274
7.1.18 RP1D—Root Port 1 Descriptor Register..................................................... 274
7.1.19 RP1BA—Root Port 1 Base Address Register............................................... 274
7.1.20 RP2D—Root Port 2 Descriptor Register..................................................... 275
7.1.21 RP2BA—Root Port 2 Base Address Register............................................... 275
7.1.22 RP3D—Root Port 3 Descriptor Register..................................................... 275
7.1.23 RP3BA—Root Port 3 Base Address Register............................................... 276
7.1.24 RP4D—Root Port 4 Descriptor Register..................................................... 276
7.1.25 RP4BA—Root Port 4 Base Address Register............................................... 276
7.1.26 HDD—Intel® High Definition Audio Descriptor Register............................... 277
7.1.27 HDBA—Intel® High Definition Audio Base Address Register......................... 277
7.1.28 RP5D—Root Port 5 Descriptor Register..................................................... 277
7.1.29 RP5BA—Root Port 5 Base Address Register............................................... 278
7.1.30 RP6D—Root Port 6 Descriptor Register..................................................... 278
7.1.31 RP6BA—Root Port 6 Base Address Register............................................... 278
7.1.32 ILCL—Internal Link Capabilities List Register ............................................ 279
7.1.33 LCAP—Link Capabilities Register ............................................................. 279
7.1.34 LCTL—Link Control Register ................................................................... 280
7.1.35 LSTS—Link Status Register .................................................................... 280
7.1.36 CIR2 — Chipset Initialization Register 2 ................................................... 280
7.1.37 CIR3 — Chipset Initialization Register 3 ................................................... 281
7.1.38 CIR4 — Chipset Initialization Register 4 ................................................... 281
7.1.39 BCR — Backbone Configuration Register .................................................. 281
7.1.40 RPC—Root Port Configuration Register ..................................................... 282
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Intel® ICH8 Family Datasheet
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