82801HB 查看數據表（PDF） - Unspecified

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82801HB

Intel® I/O Controller Hub 8 (ICH8) Family

Unspecified 

5.17

5.18

5.19

5.16.4.1 Power State Mappings.............................................................. 199

5.16.4.2 Power State Transitions............................................................ 200

5.16.4.3 SMI Trapping (APM)................................................................. 201

5.16.5 SATA LED ............................................................................................ 201

5.16.6 AHCI Operation .................................................................................... 201

5.16.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................ 202

5.16.8 SGPIO Signals ...................................................................................... 202

5.16.9 External SATA (Intel® ICH8R, ICH8DH, and ICH8DO Only) ......................... 202

High Precision Event Timers .............................................................................. 203

5.17.1 Timer Accuracy .................................................................................... 203

5.17.2 Interrupt Mapping................................................................................. 203

5.17.3 Periodic vs. Non-Periodic Modes .............................................................. 204

5.17.4 Enabling the Timers .............................................................................. 204

5.17.5 Interrupt Levels.................................................................................... 205

5.17.6 Handling Interrupts ............................................................................... 205

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 205

USB UHCI Host Controllers (D29:F0, F1, F2 and D26:F0, F1) ................................. 206

5.18.1 Data Structures in Main Memory ............................................................. 206

5.18.2 Data Transfers to/from Main Memory ...................................................... 206

5.18.3 Data Encoding and Bit Stuffing ............................................................... 206

5.18.4 Bus Protocol......................................................................................... 206

5.18.4.1 Bit Ordering............................................................................ 206

5.18.4.2 SYNC Field ............................................................................. 206

5.18.4.3 Packet Field Formats................................................................ 206

5.18.4.4 Address Fields......................................................................... 207

5.18.4.5 Frame Number Field ................................................................ 207

5.18.4.6 Data Field .............................................................................. 207

5.18.4.7 Cyclic Redundancy Check (CRC) ................................................ 207

5.18.5 Packet Formats .................................................................................... 207

5.18.6 USB Interrupts ..................................................................................... 207

5.18.6.1 Transaction-Based Interrupts .................................................... 207

5.18.6.2 Non-Transaction Based Interrupts ............................................. 209

5.18.7 USB Power Management ........................................................................ 210

5.18.8 USB Legacy Keyboard Operation ............................................................. 210

USB EHCI Host Controllers (D29:F7 and D26:F7) ................................................. 213

5.19.1 EHC Initialization .................................................................................. 213

5.19.1.1 BIOS Initialization ................................................................... 213

5.19.1.2 Driver Initialization .................................................................. 213

5.19.1.3 EHC Resets ............................................................................ 214

5.19.2 Data Structures in Main Memory ............................................................. 214

5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................... 214

5.19.4 Data Encoding and Bit Stuffing ............................................................... 214

5.19.5 Packet Formats .................................................................................... 214

5.19.6 USB 2.0 Interrupts and Error Conditions .................................................. 215

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 215

5.19.7 USB 2.0 Power Management .................................................................. 216

5.19.7.1 USB Pre-Fetch Pause Feature .................................................... 216

5.19.7.2 Suspend Feature ..................................................................... 216

5.19.7.3 ACPI Device States .................................................................. 216

5.19.7.4 ACPI System States................................................................. 217

5.19.7.5 Mobile Considerations .............................................................. 217

5.19.8 Interaction with UHCI Host Controllers..................................................... 217

5.19.8.1 Port-Routing Logic ................................................................... 217

5.19.8.2 Device Connects ..................................................................... 218

5.19.8.3 Device Disconnects.................................................................. 219

5.19.8.4 Effect of Resets on Port-Routing Logic ........................................ 219

8

Intel® ICH8 Family Datasheet

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