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9557 Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9557
8-bit I2C-bus and SMBus I/O port with reset
7.3 Register descriptions
7.3.1 Register 0 - Input port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. Writes
to this register have no effect.
Table 5. Register 0 - Input port register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
7.3.2 Register 1 - Output port register
This register reflects the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs.
In turn, reads from this register reflect the value that is in the flip-flop controlling the output
selection, not the actual pin value.
Table 6. Register 1 - Output port register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
0
0
0
0
0
0
0
0
7.3.3 Register 2 - Polarity inversion register
This register enables polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with logic 1), the corresponding port pin’s
polarity is inverted. If a bit in this register is cleared (written with logic 0), the
corresponding port pin’s original polarity is retained.
Table 7. Register 2 - Polarity inversion register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Default
1
1
1
1
0
0
0
0
7.3.4 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output.
Table 8. Register 3 - Configuration register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
1
1
1
1
1
1
1
1
PCA9557
Product data sheet
Rev. 06 — 11 June 2008
© NXP B.V. 2008. All rights reserved.
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