AD5292 查看數據表（PDF） - Analog Devices
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AD5292 Datasheet PDF : 30 Pages
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AD5291/AD5292
Data Sheet
Table 6.
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
RAB = 50 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
From 0x08C From 0x000 From 0x0B4 From 0x000
to 0x3FF
to 0x35F
to 0x3FF
to 0x31E
From 0X03C From 0x000 From 0x050 From 0x000
to 0x3FF
to 0x3C3
to 0x3FF
to 0x3AF
From 0X028 From 0x000 From 0x032 From 0x000
to 0x3FF
to 0x3D7
to 0x3FF
to 0x3CD
RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
From 0x04B From 0x000 From 0x064 From 0x000
to 0x3FF
to 0x3B4
to 0x3FF
to 0x39B
From 0x028 From 0x000 From 0x028 From 0x000
to 0x3FF
to 0x3D7
to 0x3FF
to 0x3D7
From 0x019 From 0x000 From 0x019 From 0x000
to 0x3FF
to 0x3E6
to 0x3FF
to 0x3E6
INTERFACE TIMING SPECIFICATIONS
VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
t12
t2
t3
t4
t5
t6
t7
t8
t9
t104
t114
t124
t124
t124
t124
t134
t134
t144
tRESET
tPOWER-UP5
Limit1
20
10
10
10
5
5
1
4003
14
1
40
2.4
410
8
1.5
450
1.3
450
20
2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
µs max
ns max
ms max
ms min
ns max
ms max
ns max
ns min
ms max
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
RDY low time, RDAC register write command execute time (R-Perf mode)
RDY low time, RDAC register write command execute time (normal mode)
RDY low time, memory program execute time
Software/hardware reset
RDY low time, RDAC register readback execute time
RDY low time, memory readback execute time
SCLK rising edge to SDO valid
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 50 MHz.
3 Refer to t12 and t13 for RDAC register and memory commands operations.
4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
5 Maximum time after VLOGIC is equal to 2.5 V.
DB9 (MSB)
DB0 (LSB)
0
0
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BITS
DATA BITS
Figure 2. Shift Register Content
Rev. E | Page 8 of 30
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