AD6657 查看數據表（PDF） - Analog Devices
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AD6657 Datasheet PDF : 32 Pages
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AD6657
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temperature Min
Typ
Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.2
3.6
Full
AGND − 0.3
AVDD + 0.2
Full
1.2
2.0
Full
0
0.8
Full
−10
+10
Full
−10
+10
Full
8
10
12
Full
4
CMOS
Full
0.9
Full
AGND
AVDD
Full
1.2
AVDD
Full
AGND
0.6
Full
−100
+100
Full
−100
+100
Full
12
16
20
Full
1
Full
1.22
2.1
Full
0
0.6
Full
−10
+10
Full
40
132
Full
26
Full
2
Full
1.22
Full
0
Full
−92
Full
−10
Full
26
Full
2
2.1
0.6
−135
+10
Full
1.22
2.1
Full
0
0.6
Full
−10
+10
Full
38
128
Full
26
Full
5
Unit
V
V p-p
V
V
V
μA
μA
kΩ
pF
V
V
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
Rev. B | Page 6 of 32
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