Silicore
APPLICATION CIRCUIT for MSF 50kHz
O1
O2
VDD
IC
CD1
6 . 8nF
1 . 8nF~6. 8 nF
CD2
STOP
D
Antenna L1
f R EG =50kHz
IA1
6
PON
µc
0
IA2
0
OD2
VDD=3V
VDD 2
OD1
Vc c
GND1
GND2
GND3
CD3
CDEM
CAGC
47nF
22nF
4. 7uF
D6002
APPLICATION HINT’S
The PCB has to be designed for RF conditions.
The ferrite antenna is a critical devices of the complete clock receiver.
The dimensioning of the antenna resonant resistance is a compromise between high
signal voltage and low antenna noise voltage. The Q-factor of antenna should be high
for attenuation of inference signal’s. In the application circuit is the Rref 100k,
Q=80.
To achieve a high selectivity the parasitic parallel capacitance of the crystal should be
1 ~ 1 . 5 p F.
For a trouble-free reception the capacitor on GND and CD3 have to be arranged nearby
the chip foot prints.
SHAOXING SILICORE TECHNOLOGY CO.,LTD
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