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EP1C12

Cyclone FPGA Family

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Preliminary Information

Cyclone FPGA Family Data Sheet

Logic Elements

The smallest unit of logic in the Cyclone architecture, the LE, is compact

and provides advanced features with efficient logic utilization. Each LE

contains a four-input LUT, which is a function generator that can

implement any function of four variables. In addition, each LE contains a

programmable register and carry chain with carry select capability. A

single LE also supports dynamic single bit addition or subtraction mode

selectable by an LAB-wide control signal. Each LE drives all types of

interconnects: local, row, column, LUT chain, register chain, and direct

link interconnects. See Figure 5.

Figure 5. Cyclone LE

addnsub

LAB Carry-In

Carry-In1

Carry-In0

Register chain

routing from

previous LE

LAB-wide

Synchronous

Load

LAB-wide

Synchronous

Clear

Register Bypass

Packed

Register Select

data1

data2

data3

data4

Look-Up

Table

(LUT)

Carry

Chain

Synchronous

Load and

Clear Logic

PRN/ALD

D

Q

ADATA

ENA

CLRN

labclr1

labclr2

labpre/aload

Chip-Wide

Reset

labclk1

labclk2

labclkena1

labclkena2

Asynchronous

Clear/Preset/

Load Logic

Clock &

Clock Enable

Select

Carry-Out0

Carry-Out1

LAB Carry-Out

Register

Feedback

Programmable

Register

LUT chain

routing to next LE

Row, column,

and direct link

routing

Row, column,

and direct link

routing

Local Routing

Register chain

output

Altera Corporation

9

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