HCPL-0710-500E 查看數據表（PDF） - Avago Technologies
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HCPL-0710-500E Datasheet PDF : 17 Pages
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4
3
2
1
0
0
20
40
60
80
TA (C)
Figure 4. Typical pulse width distortion vs.
temperature
15
14
13
12
0
20
40
60
80
TA (C)
Figure 5. Typical rise time vs. temperature
7
6
5
4
3
2
0
20
40
60
80
TA (C)
Figure 6. Typical fall time vs. temperature
29
27
25
23
TPLH
21
TPHL
19
17
15
15 20 25 30 35 40 45 50
CI (pF)
Figure 7. Typical propagation delays vs. output
load capacitance
6
5
4
3
2
1
0
15 20 25 30 35 40 45 50
C I (pF)
Figure 8. Typical pulse width distortion vs.
output load capacitance
25
23
21
19
17
15
13
11
9
7
5
0 5 10 15 20 25 30 35
CI (pF)
Figure 9. Typical rise time vs. load capacitance
10
9
8
7
6
5
4
3
2
1
0
0 5 10 15 20 25 30 35
CI (pF)
Figure 10. Typical fall time vs. load capacitance
STANDARD 8 PIN DIP PRODUCT
800
700
P S (mW)
IS (mA)
600
500
400
300
(230)
200
100
0
0 25 50 75 100 125 150 175 200
T A - CASE TEMPERATURE - o C
SURFACE MOUNT SO8 PRODUCT
800
700
P S (mW)
IS (mA)
600
500
400
300
200
(150)
100
0
0 25 50 75 100 125 150 175 200
T A - CASE TEMPERATURE - o C
Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per
IEC/EN/DIN EN 60747-5-5
9
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