MAX16026 查看數據表（PDF） - Unspecified

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MAX16026

Dual-/Triple-/Quad-Voltage, Capacitor Adjustable, Sequencing/Supervisory Circuits

Unspecified 

Dual-/Triple-/Quad-Voltage, Capacitor-

Adjustable, Sequencing/Supervisory Circuits

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 2.2V to 28V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

CRESET AND CDLY_

CRESET Threshold

VTH-RESET CRESET rising, VCC = 3.3V

CRESET Charge Current

ICH-RESET VCC = 3.3V

CDLY_ Threshold

VTH-CDLY CDLY_ rising, VCC = 3.3V

CDLY_ Charge Current

ICH-CDLY VCC = 3.3V

DIGITAL LOGIC INPUTS (EN_, MR, TOL, TH1, TH0)

Input Low Voltage

VIL

Input High Voltage

VIH

TH1, TH0 Logic-Input Floating

TOL, TH1, TH0 Logic-Input

Current

VTOL, VTH1, VTH0 = GND or VCC

EN_ Input Leakage Current

MR Internal Pullup Current

OUTPUTS (OUT_, RESET)

Output Low Voltage (Open-Drain

or Push-Pull)

Output High Voltage (Push-Pull)

VOL

VOH

VEN_ = VCC or GND

VCC = 3.3V

VCC ≥ 1.2V, ISINK = 90µA

VCC ≥ 2.25V, ISINK = 0.5mA

VCC ≥ 4.5V, ISINK = 1mA

VCC ≥ 3V, ISOURCE = 500µA

VCC ≥ 4.5V, ISOURCE = 800µA

Output Leakage Current (Open-

Drain)

ILKG Output not asserted low, VOUT = 28V

Reset Timeout Period

tRP

CRESET = VCC, VCC = 3.3V

CRESET open

TIMING

IN_ to OUT_ Propagation Delay

IN_ to RESET Propagation Delay

tDELAY+ IN_ rising, CDLY_ open

tDELAY- IN_ falling, CDLY_ open

tRST-DELAY IN_ falling

MIN TYP MAX UNITS

0.465 0.5 0.535

V

380 500 620

nA

0.95

1

1.05

V

200 250 300

nA

0.4

V

1.4

V

0.6

V

-1

+1

µA

-100

+100

nA

250 535 820

nA

0.8 x VCC

0.8 x VCC

0.3

0.3

V

0.35

V

1

µA

140 190 260

ms

0.030

35

µs

20

35

µs

MR Minimum Input Pulse Width

(Note 3)

2

µs

EN_ or MR Glitch Rejection

EN_ to OUT_ Delay

MR to RESET Delay

tOFF From device enabled to device disabled

tON

From device disabled to device enabled

(CDLY_ open)

MR falling

280

ns

3

µs

30

3

µs

Note 1: Devices are production tested at TA = +25°C. Limits over temperature are guaranteed by design.

Note 2: Operating below the UVLO causes all outputs to go low. The outputs are guaranteed to be in the correct state for VCC down

to 1.2V.

Note 3: In order to guarantee an assertion, the minimum input pulse width must be greater than 2µs.

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