MAX16027 查看數據表（PDF） - Unspecified
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MAX16027 Datasheet PDF : 15 Pages
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Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
Pin Description (continued)
MAX16025/
MAX16026
11
12
13
14
—
—
15
16
—
PIN
MAX16027/ MAX16029/
MAX16028 MAX16030
14
17
15
18
16
19
17
20
—
21
18
22
19
23
20
24
—
—
NAME
FUNCTION
OUT1 Output 1. When the voltage at IN1 is below its threshold or EN1 goes low,
OUT1 goes low.
RESET
Active-Low Reset Output. RESET asserts low when any of the monitored
voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is
asserted. RESET remains asserted for the reset timeout period after all of the
monitored voltages exceed their respective threshold, all EN_ are high, all
OUT_ are high, and MR is deasserted.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET
MR remains low for the reset timeout period after MR is deasserted (as long as all
OUT_ are high).
CRESET
Capacitor-Adjustable Reset Delay Input. Connect an external capacitor from
CRESET to GND to set the reset timeout period or connect to VCC for the
default 140ms minimum reset timeout period. Leave CRESET open for internal
propagation delay.
CDLY4
Capacitor-Adjustable Delay Input 4. Connect an external capacitor from
CDLY4 to GND to set the IN4 to OUT4 (and EN4 to OUT4) delay period.
Leave CDLY4 open for internal propagation delay.
CDLY3
Capacitor-Adjustable Delay Input 3. Connect an external capacitor from
CDLY3 to GND to set the IN3 to OUT3 (and EN3 to OUT3) delay period.
Leave CDLY3 open for internal propagation delay.
CDLY2
Capacitor-Adjustable Delay Input 2. Connect an external capacitor from
CDLY2 to GND to set the IN2 to OUT2 (and EN2 to OUT2) delay period.
Leave CDLY2 open for internal propagation delay.
CDLY1
Capacitor-Adjustable Delay Input 1. Connect an external capacitor from
CDLY1 to GND to set the IN1 to OUT1 (and EN1 to OUT1) delay period.
Leave CDLY1 open for internal propagation delay.
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the
ground plane.
Table 1. Output State*
EN_
IN_
OUT_
Low
High
Low
VIN_ < VTH Low
VIN_ < VTH Low
VIN_ > VTH Low
High
VIN_ > VTH
OUT_ = high
(MAX16026/MAX16028/
MAX16030)
OUT_ = high impedance
(MAX16025/MAX16027/
MAX16029)
*When VCC falls below the UVLO, all outputs go low regardless
of the state of EN_ and VIN_. The outputs are guaranteed to be
in the correct state for VCC down to 1.2V.
Table 2. Input-Voltage Threshold Selector
TH1/TH0
LOGIC
IN1 (ALL IN2 (ALL
IN3
IN4
VERSIONS) VERSIONS) (MAX16027/ (MAX16029/
(V)
(V)
MAX16028) MAX16030)
(V)
(V)
Low/Low
3.3
2.5
1.8
1.5
Low/High
3.3
1.8
Adj
Adj
Low/Open
3.3
1.5
Adj
Adj
High/Low
3.3
1.2
1.8
2.5
High/High
2.5
1.8
Adj
Adj
High/Open
3.3
Adj
2.5
Adj
Open/Low
3.3
Adj
Adj
Adj
Open/High
2.5
Adj
Adj
Adj
Open/Open
Adj
Adj
Adj
Adj
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