TC850CPL 查看數據表（PDF） - TelCom Semiconductor Inc => Microchip
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TC850CPL
TelCom Semiconductor Inc => Microchip
TC850CPL Datasheet PDF : 14 Pages
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15-BIT, FAST-INTEGRATING CMOS
ANALOG-TO-DIGITAL CONVERTER
TC850
SIGNAL
INTEGRATE
REFERENCE
DEINTEGRATE
AUTO
INTEGRATOR ZERO
OUTPUT
TIME
END OF
CONVERSION
0V
Figure 2A. Dual-Slope ADC Cycle
SIGNAL
INTERGRATE
"FAST" REFERENCE
DEINTEGRATE
(9-BIT RESOLUTION)
"SLOW" REFERENCE
DEINTEGRATE
(6-BIT RESOLUTION)
AUTO
INTEGRATOR ZERO
OUTPUT
TIME
END OF
CONVERSION
0V
Figure 2B. "Fast-Slow" Reference Deintegrate Cycle
additional 6 bits of resolution. The result is 15 bits of
resolution achieved with only 29 + 26 (512 + 64, or 576) clock
pulses for deintegration. A complete conversion cycle occu-
pies only 1280 clock pulses.
In order to generate "fast-slow" integration phases, two
voltage references are required. The primary reference
(VREF1) is set to one-half of the full-scale voltage (typically
VREF1 = 1.6384V, and VFS = 3.2768V). The secondary
voltage reference (VREF2) is set to VREF1/64 (typically 25.6
mV). To maintain 15-bit linearity, a tolerance of 0.5% for
VREF2 is recommended.
ANALOG SECTION DESCRIPTION
The TC850 analog section consists of an input buffer
amplifier, integrator amplifier, comparator, and analog
switches. A simplified block diagram is shown in Figure 3.
Conversion Timing
Each conversion consists of three phases: (1) Zero
Integrator, (2) Signal Integrate, and (3) Reference Integrate
(or Deintegrate). Each conversion cycle requires 1280 inter-
nal clock cycles (Figure 4).
IN+
COMMON
–
IN
C
+
REF1
INT
CREF1
REF1+ REF1–
C
–
REF2
C
–
REF1
DE
DE
DE
DE1 DE1
(–)
(+)
C REF2
REF2+
C
–
REF2
RINT
BUFF
DE
DE1
DE1
(–)
(+)
–
+
BUFFER*
CINT
INTIN
INTOUT
INTEGRATOR*
–
–
+
+
TO
DIGITAL
SECTION
COMPARATOR*
Z1
DE1
DE1
DE2
DE2
(+)
(–)
(+)
(–)
INT
INT
*AUTO-ZEROED
AMPLIFIERS
TC850
Figure 3. Analog Section Simplified Schematic
3-82
TELCOM SEMICONDUCTOR, INC.
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