MFRC500 查看數據表（PDF） - Unspecified

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MFRC500

Highly Integrated ISO 14443A Reader IC

Unspecified 

Philips Semiconductors

Short Form Specification Rev. 2.0 January 2002

Highly Integrated ISO 14443A Reader IC

MF RC500

2 BLOCK DIAGRAM

The block diagram shows the main internal parts

of the MF RC500.

The parallel µController interface automatically

detects the kind of 8 bit parallel interface

connected to it. It includes a comfortable bi-

directional FIFO buffer and a configurable

interrupt output. This gives the flexibility to

connect a variety of µC, even low cost devices,

still meeting the requirements of high-speed

contactless transactions.

The Data processing part performs parallel serial

conversion of the data. It supports framing

including CRC and parity generation / checking. It

operates in full transparent mode thus supporting

all layers of ISO 14443A.

The status and control part allows configuration of

the device to adapt to environmental influences

and to adjust to operate with best performance.

For communication with MIFARE® Classic

products like MIFARE® Standard or MIFARE®

Light a high speed CRYPTO 1 stream cipher unit

and a secure non-volatile key memory is

implemented.

The analog circuit includes a transmitting part with

a very low impedance bridge driver output. This

allows an operating distance up to 100mm. The

receiver is able to detect and decode even very

weak responses. Due to a highly sophisticated

implementation the receiver is no longer a limiting

factor for the operating distance.

Data Bus

Addr. Bus

Parallel

µController

Interface

with FIFO Buffer

Control Lines

MF RC500

Crypto1 Security

& Key Memory

Status and Control

Data Processing

Parallel/Serial Conversion

CRC/Parity Generation & Check

Framing Generation & Check

Bit Coding and Decoding

Analog Circuitry

Integrated

Demodulator,

Bit-Decoder,

Output Drivers

Figure 2-1: MF RC500 Block Diagram

MCIFlaAsRsiEc®

MIFARE ®

Pro

ISO14443A

4

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