LPC920F 查看數據表（PDF） - Unspecified

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LPC920F

8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM

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Table 4: Special function registers…continued

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

addr. MSB

LSB

Reset value

Hex Binary

TRIM

Internal oscillator trim register 96H

-

ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

[5] [6]

WDCON Watchdog control register

A7H PRE2 PRE1 PRE0

-

-

WDRUN WDTOF WDCLK

[4] [6]

WDL

Watchdog load

C1H

FF

11111111

WFEED1 Watchdog feed 1

C2H

WFEED2 Watchdog feed 2

C3H

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC920/921/922 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

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