LPC920F 查看數據表（PDF） - Unspecified

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LPC920F

8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM

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Philips Semiconductors

P89LPC920/921/922

8-bit microcontrollers with two-clock 80C51 core

8.6 CPU Clock (CCLK) wake-up delay

The P89LPC920/921/922 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK

cycles plus 60 to 100 µs. If the clock source is either the internal RC oscillator,

watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus

60 to 100 µs.

8.7 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC920/921/922 is designed to run at 12 MHz (CCLK) maximum. However,

if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower

the power consumption further. On any reset, CLKLP is ‘0’ allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz

or slower.

8.9 Memory organization

The various P89LPC920/921/922 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of

the Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC920/921/922 has 2 kB/4 kB/8 kB of on-chip Code

memory.

9397 750 12285

Product data

Rev. 06 — 21 November 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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