TLK3138ZDU 查看數據表（PDF） - Unspecified

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TLK3138ZDU

Dual XAUI Transceiver

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TLK3138

SLLS762A – FEBRUARY 2007 – REVISED APRIL 2007

www.ti.com

DETAILED DESCRIPTION (continued)

REDUNDANT XGMII OPERATION

The TLK3138 can operate as a redundant XGMII transceiver.

In Redundant XGMII MODE (4/5.32907.7), only the A side Serial interface is active, and both Parallel interfaces

XGMII A and XGMII B are active. It is possible for B side XAUI to transmit B side parallel data, but the receive

XAUI B interface is processed but not used. The receive datapath either duplicates the receive XAUI data to

both parallel side data streams, or if the IDLE mode is selected, send only valid (idle) sequences on the

deselected side. The transmit datapath selects one of the two aggregated input parallel streams controlled by

the A_B (4/5.32907.3) register bit.

While communication is occurring on the primary selected channel, the secondary channel is fully functional

capable of transmitting data (if desired). All B side transmit related registers are accessible and valid.

During the transition, the data on each byte of the bus is 0xFE (code violation), which is the ERROR indication,

or local fault indication (based on a provisioned register value).

RETIMER OPERATION

The TLK3138 can operate as a full duplex serial side re-timer. All the functions of transceiver operations are

performed except for the XGMII input interfaces, and optionally the XGMII output interfaces. The recovered data

on each XAUI channel is de-serialized, de-skewed, aligned to the reference clock, and re-serialized. In the

re-timer mode inputs from the XGMII inputs are ignored. XGMII outputs can provisionally be left on to snoop

received data, or turned off to save power.

Note that when RETIM is high, the serial side A receive data is routed out to the serial side B transmit serial

lines. Similarly, the serial side B receive data is routed out to the serial side A transmit serial lines.

If A/B is toggled when in re-timer monitor mode, the data on each byte of the XGMII receive output bus (if not in

3-state) is 0xFE (code violation) for several XGMII clock cycles, or local fault (based on the provisioned register

value).

PARALLEL CLOCKING MODES

The TLK3138 supports source-centered timing and source-aligned timing on the XGMII receive output bus. The

source-centered timing supported is the timing defined in P802.3ae Clause 46, with the RX_CLK centered within

the receive output data bit timing, as shown in Figure 12. Also shown is source-aligned timing.

RX_CLK

tSETUP

Source Centered (DDR)

tHOLD

RXD(31:0)

RXC(3:0)

Source Aligned (DDR)

Data

RXD(31:0)

RXC(3:0)

Data

Data

tSETUP

tHOLD

Data

Data

Figure 12. Receive Interface Timing – Source Centered/Aligned

On the transmit data path, the data is sampled on the rising edge and falling edge of TCLK as shown in

Figure 13.

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