TLK3138ZDU 查看數據表（PDF） - Unspecified

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TLK3138ZDU

Dual XAUI Transceiver

Unspecified 

www.ti.com

Parallel Data In

Parallel

to

Serial

REFCLKP

/N

Multiplying

Clock

Synthesizer

Baud

Clock

TLK3138

SLLS762A – FEBRUARY 2007 – REVISED APRIL 2007

DQ

TDP

TDN

RCLK

Interpolator

and Clock

Recovery

Recovered

Clock

Parallel Data Out

Serial to

Parallel

and

Comma

Detect

RDP

RDN

Figure 11. Block Diagram of SERDES Core

DETAILED DESCRIPTION

The TLK3138 has several operational interface modes controlled by register bits A/B and XAUI_RETIME,

REDUNDANT_XAUI, and REDUNDANT_XGMII. The major modes of application are discussed below.

REDUNDANT XAUI OPERATION

The TLK3138 can operate as a redundant XAUI transceiver.

In Redundant XAUI MODE (4/5.32907.6), only the A side XGMII interface is active, and both serial interfaces

XAUI A and XAUI B are active. It is possible for B side XGMII to receive B side serial data, but the transmit

XGMII B interface is ignored. The transmit datapath either duplicates the transmit XGMII data to both serial side

data streams, or if the IDLE mode is selected, send only valid A/K/R (idle) sequences on the deselected side.

The receive datapath selects one of the two aggregated input serial streams controlled by the A_B (4/5.32907.3)

register bit.

While communication is occurring on the primary selected channel, the secondary channel is fully functional

capable of transmitting and receiving data. All registers are accessible and valid. The only difference between

the primary and secondary channels is the primary channel is routed to the A side XGMII receive bus.

A completely active secondary channel allows transition from primary to secondary channels within a few clock

cycles. During the transition, the data on each byte of the bus is 0xFE (code violation), which is the ERROR

indication, or local fault indication (based on a provisioned register value).

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