NTD40N03R 查看數據表（PDF） - ON Semiconductor
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NTD40N03R Datasheet PDF : 8 Pages
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NTD40N03R
1000
Ciss
800
VDS = 0 V VGS = 0 V
Crss
600
TJ = 25°C
Ciss
400
Coss
200
Crss
0
10
5 VGS 0 VDS 5
10
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
100
VDS = 10 V
ID = 10 A
VGS = 10 V
tr
td(off)
10
td(on)
tf
1
1
10
100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
8
6
4
Q1
QT
Q2
VGS
2
ID = 10 A
TJ = 25°C
0
0
2
4
6
8
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
20
18 VGS = 0 V
16 TJ = 25°C
14
12
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus
Current
100
SINGLE PULSE
VGS = 20 V
TC = 25°C
10 ms
100 ms
10
1 ms
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
10 ms
dc
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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