74VHC138SJ 查看數據表（PDF） - Fairchild Semiconductor

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74VHC138SJ

3-to-8 Decoder/Demultiplexer

Fairchild Semiconductor 

November 1992

Revised April 1999

74VHC138

3-to-8 Decoder/Demultiplexer

General Description

The VHC138 is an advanced high speed CMOS 3-to-8

decoder/demultiplexer fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

When the device is enabled, 3 binary select inputs (A0, A1

and A2) determine which one of the outputs (O0–O7) will go

LOW. When enable input E3 is held LOW or either E1 or E2

is held HIGH, decoding function is inhibited and all outputs

go HIGH. E3, E1 and E2 inputs are provided to ease cas-

cade connection and for use as an address decoder for

memory systems. An input protection circuit ensures that

0V to 7V can be applied to the input pins without regard to

the supply voltage. This device can be used to interface 5V

to 3V systems and two supply systems such as battery

back up. This circuit prevents device destruction due to

mismatched supply and input voltages.

Features

s High Speed: tPD = 5.7ns (typ) at TA = 25°C

s Low power dissipation: ICC = 4 µA (max.) at TA = 25°C

s High noise immunity: VNIH = VNIL = 28% VCC (min.)

s Power down protection provided on all inputs

s Pin and function compatible with 74HC138

Ordering Code:

Order Number Package Number

Package Description

74VHC138M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC138SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC138MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC138N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

A0–A2

E1–E2

E3

O0–O7

Description

Address Inputs

Enable Inputs

Enable Input

Outputs

© 1999 Fairchild Semiconductor Corporation DS011537.prf

www.fairchildsemi.com

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