HFBR-53D5 查看數據表（PDF） - Avago Technologies

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HFBR-53D5

1 x 9 Fiber Optic Transceivers for Gigabit Ethernet

Avago Technologies 

10

Table 1. Pinout Table

Pin Symbol

Mounting Pins

1

VEER

2

RD+

3

RD–

4

SD

5

VCCR

6

VCCT

7

TD–

8

TD+

9

VEET

Functional Description

The mounting pins are provided for transceiver mechanical attachment to the circuit

board. They are embedded in the nonconductive plastic housing and are not connected

to the transceiver internal circuit, nor is there a guaranteed connection to the metallized

housing in the EM and FM versions. They should be soldered into plated-through holes

on the printed circuit board.

Receiver Signal Ground

Directly connect this pin to receiver signal ground plane. (For HFBR-53D5, VEER = VEET)

Receiver Data Out

RD+ is an open-emitter output circuit. Terminate this high-speed differential PECL

output with standard PECL techniques at the follow-on device input pin.

Receiver Data Out Bar

RD– is an open-emitter output circuit. Terminate this high-speed differential PECL

output with standard PECL techniques at the follow-on device input pin.

Signal Detect

Normal optical input levels to the receiver result in a logic “1” output, VOH, asserted.

Low input optical levels to the receiver result in a fault condition indicated by

a logic “0” output VOL, deasserted.

Signal Detect is a single-ended PECL output. SD can be terminated with standard PECL

techniques via 50 Ω to VCCR - 2 V. Alternatively, SD can be loaded with a 270 Ω resistor

to VEER to conserve electrical power with small compromise to signal quality. If Signal

Detect output is not used, leave it open-circuited.

This Signal Detect output can be used to drive a PECL input on an upstream circuit,

such as, Signal Detect input or Loss of Signal-bar.

Receiver Power Supply

Provide +5 Vdc via the recommended receiver power supply filter circuit.

Locate the power supply filter circuit as close as possible to the VCCR pin.

Transmitter Power Supply

Provide +5 Vdc via the recommended transmitter power supply filter circuit.

Locate the power supply filter circuit as close as possible to the VCCT pin.

Transmitter Data In-Bar

Terminate this high-speed differential PECL input with standard PECL techniques at the

transmitter input pin.

Transmitter Data In

Terminate this high-speed differential PECL input with standard PECL techniques at the

transmitter input pin.

Transmitter Signal Ground

Directly connect this pin to the transmitter signal ground plane.

1.3

1.0

0.8

0.5

0.2

0

-0.2

0 0.22 0.375

0.625 0.78 1.0

NORMALIZED TIME

Figure 1. Transmitter Optical Eye Diagram Mask.

1 = VEER

2 = RD+

3 = RD-

4 = SD

5 = VCCR

6 = VCCT

7 = TD-

8 = TD+

9 = VEET

NIC

RX

TX

NIC

TOP VIEW

NIC = NO INTERNAL CONNECTION (MOUNTING PINS)

Figure 2. Pin-Out.

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