HFBR-53D5 查看數據表（PDF） - Avago Technologies

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HFBR-53D5

1 x 9 Fiber Optic Transceivers for Gigabit Ethernet

Avago Technologies 

11

LASER

DRIVER

CIRCUIT

C5

0.1 µF

VEET 9

8

TD+

5 Vdc

R3 R2

68 68

50 Ω

C9 0.01 µF

PECL

INPUT

TD- 7

50 Ω

C10 0.01 µF

R4 R1

R13

191 191

150

HFBR/HFCT-53D5

FIBER-OPTIC

TRANSCEIVER

VCCT 6

VCCR 5

L2

C2

1 µH

0.1 µF

L1

C1 + C8* 1 µH

0.1

10 µF*

µF

5 Vdc

C3 + C4

0.1

10

µF

µF

3.3 Vdc

+

GND

VCC2 VEE2

TD+

OUTPUT

DRIVER

TD-

R12

150

CLOCK

SYNTHESIS

CIRCUIT

PARALLEL

TO SERIAL

CIRCUIT

HDMP-1636A/-1646A

SERIAL/DE-SERIALIZER

(SERDES - 10 BIT

TRANSCEIVER)

SIGNAL

DETECT

SD 4

CIRCUIT

R9

TO SIGNAL DETECT (SD)

INPUT AT UPPER-LEVEL-IC

PRE-

AMPLIFIER

RD- 3

POST-

AMPLIFIER

RD+ 2

VEER 1

270

R11 R10

270 270

C12 0.01 µF

C11 0.01 µF

50 Ω

R14

100

50 Ω

RD-

INPUT

BUFFER

RD+

CLOCK

RECOVERY

CIRCUIT

SERIAL TO

PARALLEL

CIRCUIT

SEE HDMP-1636A/-1646A DATA SHEET FOR

DETAILS ABOUT THIS TRANSCEIVER IC.

NOTES:

*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.

USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.

USE 50 Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.

LOCATE 50 Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.

Figure 3. Recommended Gigabit/sec Ethernet HFBR/HFCT-53D5 Fiber-Optic Transceiver and HDMP-1636A/1646A

SERDES Integrated Circuit Transceiver Interface and Power Supply Filter Circuits.

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