FS6011-02 查看數據表（PDF） - AMI Semiconductor
零件编号
产品描述 (功能)
生产厂家
FS6011-02 Datasheet PDF : 15 Pages
| |||
)6
'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU ,&
X T
July 1998
4.1 Audio PLL Clock Frequencies (ACLK)
The ACLK frequency is controlled by register bits D[0],
D[1], and D[2] accessed via the serial interface. The
ACLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
4.3 Utility PLL Clock Frequencies (UCLK)
The UCLK frequency is controlled by register bits D[5],
D[6] and D[7], accessed via the serial interface. UCLK
frequencies listed below are derived via the PLL Divider
Ratio from a reference frequency of 27MHz.
Table 3: ACLK Frequency Select
D[2]
D[1]
D[0]
PLL DIVIDER
AUDIO
RATIO OVERSAMPLING
0
0
0 1024 / 2250
48kHz x 256
0
0
1 1024 / 3375
32kHz x 256
0
1
0 1024 / 4500 48kHz x 256 / 2
0
1
1 1024 / 6750 32kHz x 256 / 2
1
0
0 1568 / 3750 44.1kHz x 256
1
0
1 1568 / 2500 44.1kHz x 384
1
1
0 1568 / 7500 44.1kHz x 256 / 2
1
1
1 1024 / 1125
NOTE: Contact AMI for custom PLL frequencies
48kHz x 512
ACLK
(MHz)
12.288
8.192
6.144
4.096
11.2896
16.9344
5.6448
24.576
Table 5: UCLK Frequency Select
D[7] D[6] D[5] PLL DIVIDER RATIO
0
0
0
16 / 27
0
0
1
35 / 33
0
1
0
1568 / 3750
0
1
1
1
1
0
0
544 / 375
1
0
1
728 / 375
1
1
0
10 / 9
1
1
1
1024 / 1125
NOTE: Contact AMI for custom PLL frequencies
UCLK (MHz)
16.0000
28.6363
11.2896
27.0000
39.1680
52.4160
30.0000
24.5760
4.2 Audio Clock Off-Speed Frequencies
The ACLK frequencies shown may be smoothly modified
to a slightly higher or lower value under register control.
Register bit D[3] must be a logic-one to activate this
mode. The value of D[4] controls whether the frequency
will be adjusted slightly low (D[4] = 0) or high (D[4] = 1).
4.4 Processor PLL Frequencies (PCLK)
The PCLK frequency is controlled by the logic levels on
the PSEL0 and PSEL1 inputs. These inputs have weak
pull-downs. PCLK frequencies listed below are derived
via the PLL Divider Ratio from a reference frequency of
27MHz.
Table 4: Audio Off Speed Frequencies
D[4]
D[3]
D[2]
D[1]
D[0]
PLL DIVIDER
RATIO
0
1
0
0
0
1023 / 2250
0
1
0
0
1
1023 / 3375
0
1
0
1
0
1023 / 4500
0
1
0
1
1
1023 / 6750
0
1
1
0
0
1567 / 3750
0
1
1
0
1
1567 / 2500
0
1
1
1
0
1567 / 7500
0
1
1
1
1
1023 / 1125
1
1
0
0
0
1025 / 2250
1
1
0
0
1
1025 / 3375
1
1
0
1
0
1025 / 4500
1
1
0
1
1
1025 / 6750
1
1
1
0
0
1569 / 3750
1
1
1
0
1
1569 / 2500
1
1
1
1
0
1569 / 7500
1
1
1
1
1
1025 / 1125
ACLK
(MHz)
12.276
8.184
6.138
4.092
11.2824
16.9236
5.6412
24.5520
12.3000
8.2000
6.1500
4.1000
11.2968
16.9432
5.6484
24.6000
Table 6: PCLK Frequency Select
PSEL1 PSEL0 PLL DIVIDER RATIO
0
0
32 / 27
0
1
40 / 27
1
0
50 / 27
1
1
60 / 41
NOTE: Contact AMI for custom PLL frequencies
PCLK (MHz)
32.0000
40.0000
50.0000
39.5122
4
,62
7.20.98
Share Link: 