FS6232-01 查看數據表（PDF） - AMI Semiconductor
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FS6232-01 Datasheet PDF : 14 Pages
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FS6232-01
Two-Way MP Motherboard Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
September 2000
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
25
DIO
26
DIO
35, 34, 31, 30 DO
50, 51
AO
47, 48
AO
44, 45
AO
41, 42
AO
39
AI
54
DO
55
DO
8, 9, 11, 12,
14, 15, 17, 18, DO
20, 21
28
DI
2
DIO
3
DIO
23
DI
NAME
CK48_0
SEL_A
CK48_1
SEL_B
CK66_0:3
HOST_P1
HOST_N1
HOST_P2
HOST_N2
HOST_P3
HOST_N3
HOST_P4
HOST_N4
IREF
MREF_N
MREF_P
DESCRIPTION
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
Host clock pair #2; one of six pairs of current-steering differential current-mode outputs
Host clock pair #3; one of six pairs of current-steering differential current-mode outputs
Host clock pair #4; one of six pairs of current-steering differential current-mode outputs
A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
One clock in a pair of outputs provided as a reference clock to a memory clock driver
PCI_0:9 Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns
PWR_DWN#
REF_0
ISEL_0
REF_1
ISEL_1
SEL133/100#
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency
SUPPLY
VDD_48
VDD_48
VDD_66
VDD_H
VDD_H
VDD_H
VDD_H
VDD
VDD_M
VDD_M
VDD_P
VDD_48
VDD_R
VDD_R
VDD_48
52
DI
SS_EN# Active low spread-spectrum enable turns on spread spectrum modulation
VDD_M
38
P
27
P
29, 36
P
43, 49
P
56
P
10, 16, 22
P
4
P
37
P
24
P
32, 33
P
40, 46
P
53
P
7, 13, 19
P
1
P
5
AI
6
AO
VDD
VDD_48
VDD_66
VDD_H
VDD_M
VDD_P
VDD_R
VSS
VSS_48
VSS_66
VSS_H
VSS_M
VSS_P
VSS_R
XIN
XOUT
3.3V core power supply
3.3V power supply for CK48 clock outputs
3.3V power supply for CK66 clock outputs
3.3V power supply for the differential HOST clock outputs
3.3V power supply for MREF clock outputs
3.3V power supply for PCI clock outputs
3.3V power supply for the REF clock output and the crystal oscillator
Core ground
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the differential HOST clock outputs
Ground for the MREF clock outputs
Ground for the PCI clock outputs
Ground for the REF clock outputs and the crystal oscillator
14.318MHz crystal oscillator input
14.318MHz crystal oscillator output
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD_R
VDD_R
ISO9001
2
9.18.00
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