FS612510-01 查看數據表（PDF） - AMI Semiconductor
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FS612510-01 Datasheet PDF : 8 Pages
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AMERICAN MICROSYSTEMS, INC.
FS612510-01/-02
1:10 Zero-Delay Clock Buffer IC
November 2000
3.0 Device Operation
The FS612510 is a zero-delay buffer intended for use on
buffered PC133 SDRAM DIMMs.
The FS612510 precisely aligns the frequency and phase
of the output clocks to the input CLK by use of an on-chip
phase-lock loop (PLL). The PLL generates up to 10 low-
skew, low-jitter copies of the CLK, with the outputs ad-
justed for 50% duty cycle.
The FBOUT clock must be hardwired to the FBIN pin to
complete the loop. The PLL actively adjusts the output
clocks so that there is no phase error between the refer-
ence clock (CLK) and the feedback clock (FBIN).
Since the device uses a PLL to lock the output clocks to
the input clock, there is a power-up stabilization time that
is required for the PLL to achieve phase lock.
Note that all inputs and outputs use LVCMOS signal lev-
els.
3.1 PLL Bypass
When the AVDD pin is pulled low, the reference clock
signal bypasses the PLL and is muxed directly through to
the outputs. The PLL is powered down, and device acts a
fanout buffer.
Note that if AVDD is re-established, the PLL requires a
power-up and stabilization time to lock to the input clock.
3.2 Output Enable/Disable
All ten outputs are enabled or disabled as a group by the
G enable signal.
A logic-high on G input enables all the clock outputs to
swing in phase with the reference clock. A logic-low on G
forces all of the clock outputs to a logic-low state.
The function table Table 1 shows the effect of the G en-
able signal on the clock outputs.
3.3 Power-Down
The FS612510-02 version provides an auto power-down
feature that shuts off the PLL, drives all outputs low, and
places the device into a low current state if the reference
clock stops. The power-down circuit is level sensitive,
and detects either a DC high or low on the CLK input.
4.0 Tracking Skew
PLL-based buffer ICs may be required to follow a spread-
spectrum modulated reference clock for frequencies
greater than 66MHz. Spread spectrum modulation limits
peak EMI emissions by intentionally introducing jitter onto
a clock signal, effectively spreading the peak energy over
a range of frequencies.
A downstream PLL, contained in a clock buffer IC such
as this one, must carefully track the modulated input ref-
erence clock. A measure of how closely the downstream
PLL follows the modulated clock is called the tracking
skew. To ensure a tight tracking skew, the loop band-
width of a downstream PLL is increased and the loop
phase angle is reduced over that of typical PLL-based
clock generators.
The type of modulation profile used impacts tracking
skew. The maximum frequency change occurs at the
profile limits where the modulation changes the slew rate
polarity. To track the sudden reversal in clock frequency,
the downstream PLL must have a large loop bandwidth.
The ability of the downstream PLL to catch up to the
modulating clock is determined by the loop transfer func-
tion phase angle.
The spread-spectrum reference clock should be either a
triangle-wave or a non-linear (Lexmark) modulation pro-
file, with a modulation frequency of 50kHz or less.
ISO9001
QS9000
3
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