FS6012-02 查看數據表（PDF） - AMI Semiconductor
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FS6012-02 Datasheet PDF : 20 Pages
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August 1998
4.1 Audio PLL Clock Frequencies (ACLK)
The ACLK frequency is controlled by register bits D[0],
D[1], D[2], and D[3], accessed via the serial interface.
ACLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
Table 3: ACLK Frequency Select via I2C-bus
D[3] D[2] D[1] D[0] PLL DIVIDER RATIO ACLK (MHz)
0000
32 / 27
32.0000
0001
784 / 1875
11.2896
0010
512 / 1875
7.3728
0011
128 / 1875
1.8432
0100
8/9
24.0000
0101
1
27.0000
0110
823 / 1968
11.2912
0111
461 / 1688
7.3738
1000
99 / 1450
1.8434
1001
809 / 910
24.0033
1010 to 1111
Duplicate of 0010 to 0111 selections
NOTE: Contact AMI for custom PLL frequencies
4.2 Utility PLL Clock Frequencies (UCLK)
The UCLK frequency is controlled by register bits D[4],
D[5], D[6] and D[7], accessed via the serial interface.
UCLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
4.3 Processor PLL Frequencies (PCLK)
The PCLK frequency is controlled by either the logic lev-
els on the PSEL inputs or through bits D[10:8]. PCLK fre-
quencies listed below are derived via the PLL Divider Ra-
tio from a reference frequency of 27MHz. These inputs
have weak pull-downs.
Table 5: PCLK Frequency Select via Pins
ADDR PSEL1 PSEL0 PLL DIVIDER RATIO PCLK (MHz)
0
0
0
35 / 66
14.31818
0
0
1
423 / 644
17.73447
0
1
0
35 / 264
3.579545
0
1
1
See Table 6
1
0
0
427 / 2600
4.43423
1
0
1
423 / 2576
4.433618
1
1
0
1135 / 6912
4.4335937
1
1
1
NOTE: Contact AMI for custom PLL frequencies
See Table 6
For the special case where both PSEL inputs are high,
the PCLK frequency is controlled by data bits D[10:8].
PCLK frequencies listed below are derived via the PLL
Divider Ratio from a reference frequency of 27MHz.
Table 6: PCLK Frequency Select via I2C-bus
Table 4: UCLK Frequency Select via I2C-bus
D[7] D[6] D[5] D[4] PLL DIVIDER RATIO UCLK (MHz)
0000
32 / 27
32.0000
0001
34 / 143
6.4196
0010
68 / 143
12.8392
0011
488 / 2025
6.5067
0100
976 / 2025
13.0133
0101
13 / 54
6.5000
0110
13 / 27
13.0000
0111
10 / 11
24.5454
1000
1
27.0000
1001
10 / 33
8.1818
1010 to 1111
Duplicate of 0010 to 0111 selections
NOTE: Contact AMI for custom PLL frequencies
D[10] D[9] D[8] PLL DIVIDER RATIO
0
0
0
35 / 66
0
0
1
423 / 644
0
1
0
35 / 264
0
1
1
728 / 375
1
0
0
427 / 2600
1
0
1
423 / 2576
1
1
0
1135 / 6912
1
1
1
18 / 25
NOTE: Contact AMI for custom PLL frequencies
PCLK (MHz)
14.3182
17.7345
3.5795
52.4160
4.4342
4.43361
4.43359
19.4400
,62
4
8.19.98
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