11995-202 查看數據表（PDF） - AMI Semiconductor

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11995-202

Motherboard Clock Generator IC

AMI Semiconductor 

FS6233-01

Motherboard Clock Generator IC

AMERICAN MICROSYSTEMS, INC.

September 2000

Table 3: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active-low pin

PIN

48

24

30, 29, 27

41, 40

38, 37

35

44

45

6, 7, 9, 10,

12, 13, 15,

16, 18, 19

32

2

1

21

42

34

25

26, 31

39

46

8, 14, 20

2

33

22

28

36

43

5, 11, 17

47

3

4

TYPE

DIO

DIO

DO

AO

AO

AI

DO

DO

NAME

CK48_0

SEL_A

CK48_1

SEL_B

CK66_0:3

HOST_P1

HOST_N1

HOST_P2

HOST_N2

IREF

MREF_N

MREF_P

DESCRIPTION

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

One of two latched inputs that select the HOST and MREF output frequency

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

One of two latched inputs that select the HOST and MREF output frequency

Three 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL

Host clock pair #1; one of two pairs of current-steering differential current-mode outputs. The

current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1

Host clock pair #2; one of two pairs of current-steering differential current-mode outputs

A fixed precision resistor from this pin to ground provides a reference current used for the dif-

ferential current-mode HOST clock outputs

One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock

to a memory clock driver

One clock in a pair of outputs provided as a reference clock to a memory clock driver

SUPPLY

VDD_48

VDD_48

VDD_66

VDD_H

VDD_H

VDD

VDD_M

VDD_M

DO

PCI_0:9 Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns

VDD_P

DI

PWR_DWN#

Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all

clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.

VDD_48

REF_0

One of two 3.3V buffered copies of the crystal reference frequency clock

DIO

ISEL_0

One of two latched inputs that select the multiplying factor of the IREF reference current for the VDD_R

HOST pair outputs

REF_1

One of two 3.3V buffered copies of the crystal reference frequency clock

DIO

ISEL_1

One of two latched inputs that select the multiplying factor of the IREF reference current for the VDD_R

HOST pair outputs

DI SEL133/100# Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency

VDD_48

DI

SS_EN# Active low spread-spectrum enable turns on spread spectrum modulation

VDD_M

P

VDD

3.3V core power supply

-

P

VDD_48 3.3V power supply for CK48 clock outputs

-

P

VDD_66 3.3V power supply for CK66 clock outputs

-

P

VDD_H 3.3V power supply for the differential HOST clock outputs

-

P

VDD_M 3.3V power supply for MREF clock outputs

-

P

VDD_P 3.3V power supply for PCI clock outputs

-

P

VDD_R 3.3V power supply for the REF clock output and the crystal oscillator

-

P

VSS

Core ground

-

P

VSS_48 Ground for the CK48 clock outputs

-

P

VSS_66 Ground for the CK66 clock outputs

P

VSS_H Ground for the differential HOST clock outputs

-

P

VSS_M Ground for the MREF clock outputs

-

P

VSS_P Ground for the PCI clock outputs

-

P

VSS_R Ground for the REF clock outputs and the crystal oscillator

-

AI

XIN

14.318MHz crystal oscillator input

VDD_R

AO

XOUT

14.318MHz crystal oscillator output

VDD_R

ISO9001

2

9.18.00

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