FS6131-01
Programmable Line Lock Clock Generator IC
Figure 13: Random Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
START
Command
WRITE Command
From bus host
to device
From device
to bus host
STOP Condition
Acknowledge
Figure 14: Random Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
STOP Condition
NO Acknowledge
Figure 15: Sequential Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A
DATA
A
DATA
A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
Data
Acknowledge
START
Command
WRITE Command
From bus host
to device
From device
to bus host
Data
Acknowledge
Figure 16: Sequential Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A
DATA
Acknowledge
Data
Acknowledge
STOP Command
A
DATA
AP
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
7-bit Receive
Device Address
Repeat START
Acknowledge
From device
to bus host
Data
Acknowledge
READ Command
11
Acknowledge
Data
NO Acknowledge
STOP Command