11274-901 查看數據表（PDF） - AMI Semiconductor
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11274-901 Datasheet PDF : 39 Pages
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FS6131-01
Programmable Line Lock Clock Generator IC
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4 Feedback Divider Monitoring
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the STAT[1] and STAT[0] bits to one. The
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
4.3 Loop Gain Analysis
For applications where an external loop filter is required,
the following analysis example can be used to determine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Set the charge pump current: I chgpump = 10µA
Set the loop filter values:
RLF = 15kΩ
C1 = 0.015µF
C2 = 220 pF
Set the VCO gain (VCOSPD): AVCO = 230MHz /V
Set the Feedback Divider:
N F = 3500
Set the Reference frequency (at the input to the Phase
Detector:
f REF = 20kHz
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
K PD
=
I chgpump
2π
The transfer function of the loop filter is (in V/A):
K LF
(s)
=
sC2
çæ
+ç
ççè
1
1
÷ö
÷
RLF + çèæ 1sC1 ÷øö ÷÷ø
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
KVCO
(s)
=
2πAVCO
1
s
The transfer function of the Feedback Divider is:
KF
=
1
NF
Finally, the sampling effect that occurs in the Phase De-
tector is accounted for by:
K SAMP (s)
=
çæ1 −
ç
çè
e −çèæ s
s
f REF
÷øö
÷ö
÷
÷ø
f REF
The loop gain of the PLL is:
K LOOP (s) = K PD K LF (s)KVCO (s)K F K SAMP (s)
Figure 8: Loop Gain vs. Frequency
100
10
1
0.1
0.01
0.1kHz
1kHz
10kHz
Frequency (fi)
100kHz
5
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