IMP1232LP 查看數據表（PDF） - IMP, Inc
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IMP1232LP Datasheet PDF : 7 Pages
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IMP1232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
ST Pulses as short as 20ns can be detected.
Valid
Valid
Invalid
Strobe
Strobe
Strobe
ST
tRST
RESET
tST
tTD
(Min)
tTD
(Max)
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
TD Voltage Level
Watchdog Time-Out Period (ms)
Min
Nominal
Max
GND
62.5
150
250
Floating
250
610
1000
VCC
500
1200
2000
1232_t03.eps
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
1232_09.eps
5V
IMP1232LP/LPS
1
PBRST
2
TD
8
VCC
7
ST
3
6
TOL RESET
4
5
GND RESET
10kΩ
µP
RESET
MREQ
Address
Bus
Figure 6. Application Circuit: Watchdog Timer
Decoder
1232_07.eps
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
5
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