KE5BLME064 查看數據表（PDF） - KAWASAKI MICROELECTRONICS
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KE5BLME064 Datasheet PDF : 53 Pages
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Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064)
PRELIMINARY
3.3 Pin Description
Pin Name Attribute
Description
#of
Pins
CLK
Clock
CLK is the master clock input. Input
1
Input
signals refer to the rising edge of CLK.
LVTTL
SRCHN Search Enable
SRCHN enables a search operation;
1
Input
search commences when Low is
LVTTL
signaled.
INP
Input Bus
INP<39:0> is a 40-bit input bus used
40
<39:0> Input
search key inputs.
LVTTL
OUT
Output Bus
OUT<17:0>, a 18-bit output bus,
18
<17:0> Output
outputs the associate data.
LVTTL
OEN
Output Enable
OEN controls OUT<17:0>. OEN
1
Input
Low enables OUT<17:0> ; and OEN
LVTTL
High enables High-Z.
ODONEN Output DONE
ODONEN Low Active indicates that
1
Output
the associate data is output to the OUT
LVTTL
<18:0> after a search.
HON
Hit Output
HON outputs a search result.
1
Output
Low indicates a hit; High indicates a
LVTTL
miss hit.
MLE
Match Length
MLE outputs match-length
6
<5:0> Output
information (prefix lengh-1) between
LVTTL
the data stored in the table and the
relevant search key.
MLOEN Match Length Output Enable
MLOEN controls MLE<5:0> Output
1
Input
Enable. Low enables MLE<5:0>;
LVTTL
High changes it to High-Z.
MDONEN MLE Done
MDONEN Low indicates that the
1
Output
completion of the search, outputting
LVTTL
the match length to MLE<5:0>.
RSTN Reset
RSTN input Low resets the hardware.
1
Input
LVTTL
IRQN Interrupt Request
IRQN indicates Low when an interrupt
1
Output
condition occurs in the CNTL register.
Open Drain
CCMPN Command Execution Completion
CCMPN signals High during the
1
Output
command operation executed via CPU
LVTTL
port, and signals Low upon the
completion of its execution.
ADD
CPU Port Address
ADD<3:0> is a register address.
4
<3:0> Input
LVTTL
DAT
CPU Port Data Bus
DAT<15:0> is an input/output data bus
16
<15:0> Input/Output
for a CPU port.
LVTTL
Version 2.5.4
Proprietary and Confidential
6
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