FDC87W22 查看數據表（PDF） - SMSC -> Microchip

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FDC87W22

Power I/O Controller

SMSC -> Microchip 

TABLE OF CONTENTS

FEATURES ....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................ 2

PIN CONFIGURATION...................................................................................................................... 5

PIN DESCRIPTION .......................................................................................................................... 6

HOST INTERFACE.............................................................................................................................. 6

SERIAL PORT INTERFACE ................................................................................................................... 7

GAME PORT/POWER DOWN INTERFACE ............................................................................................... 9

MULTI-MODE PARALLEL PORT .......................................................................................................... 10

IDE AND FDC INTERFACE ............................................................................................................... 18

FDC FUNCTIONAL DESCRIPTION................................................................................................. 20

FDC87W22 FDC.......................................................................................................................... 20

AT INTERFACE ............................................................................................................................... 20

FIFO (DATA)................................................................................................................................. 20

DATA SEPARATOR .......................................................................................................................... 21

WRITE PRECOMPENSATION .............................................................................................................. 21

PERPENDICULAR RECORDING MODE .................................................................................................. 21

FDC CORE ................................................................................................................................... 22

FDC COMMANDS............................................................................................................................ 23

REGISTER DESCRIPTIONS................................................................................................................. 32

STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0) .......................................................... 33

STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1) .......................................................... 35

DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2) ............................................... 37

TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3) ........................................................ 37

MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4) ..................................................... 38

DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4) ...................................................... 39

FIFO REGISTER (R/W BASE ADDRESS + 5)........................................................................................ 40

STATUS REGISTER 0 (ST0).............................................................................................................. 41

STATUS REGISTER 1 (ST1).............................................................................................................. 41

STATUS REGISTER 2 (ST2).............................................................................................................. 42

STATUS REGISTER 3 (ST3).............................................................................................................. 42

DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7)...................................................... 42

CONFIGURATION CONTROL REGISTER (CC REGISTER) (WRITE BASE ADDRESS + 7) ................................. 44

IDE.................................................................................................................................................. 45

IDE DECODE DESCRIPTION .............................................................................................................. 45

UART PORT ................................................................................................................................... 46

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................................ 46

UART CONTROL REGISTER (UCR) (READ/WRITE) ............................................................................. 49

UART STATUS REGISTER (USR) (READ/WRITE)................................................................................ 50

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