SSD0817Z(2002) 查看數據表（PDF） - Solomon Systech

零件编号

产品描述 (功能)

生产厂家

SSD0817Z
(Rev.:2002)

LCD Segment / Common Driver with Controller

Solomon Systech  

FUNCTIONAL BLOCK DESCRIPTIONS

IIC communication Interface

The IIC communication interface consists of slave address bit (SA0), I2C-bus data signal (SDA) and I2C-

bus clock signal (SCL). Both the SDA and the SCL must be connected to pull-up resistors. There are also

five input signals including, RES , CS1, IIC1, CS2, IIC2, which is used for the initialization of device.

a) Slave address bit (SA0)

SSD0817 have to recognize the slave address before transmitting or receiving any information by

the I2C-bus. The device will responds to the slave address following by the slave address bit

(“SA0” bit) and the read/write select bit (“R/W ” bit) with the following byte format,

b7 b6 b5 b4 b3 b2 b1 b0

0 1 1 1 1 0 SA0 R/W

“SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101”, can be

selected as the slave address of SSD0817.

“R/W ” bit determines the I2C-bus interface is operating at either write mode or read status mode.

b) I2C-bus data signal (SDA)

SDA acts as a communication channel between the transmitter and the receiver. The data and

the acknowledgement are sent through the SDA. If SDA in is connected to the “SDA out”, the

device becomes fully IIC bus compatible.

It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin

becomes a voltage potential divider. As a result, the acknowledgement would not be possible to

attain a valid logic 0 level in “SDA”.

The “SDA out” pin may be disconnected from the “SDA in” pin. With such arrangement, the

acknowledgement signal will be ignored in the I2C-bus.

c) I2C-bus clock signal (SCL)

The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission

of data bit is taken place during a single clock period of SCL.

Command Decoder

Input is directed to the command decoder based on the input of control byte which consists of a D/ C bit

and a R/W bit. For further information about the control byte, please refer to the section “I2C-bus Write

data and read register status” on page 21. If both the D/ C bit and the R/W bit are low, the input signal is

interpreted as a Command. It will be decoded and written to the corresponding command register. If the

D/ C bit is high and the R/W bit is low, input signal is written to Graphic Display Data RAM (GDDRAM).

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is

104 x 65 = 6760 bits. Table 4 on Page 12 is a description of the GDDRAM address map. For mechanical

flexibility, re-mapping on both Segment and Common outputs can be selected by software.

During the vertical scrolling of the display, an internal register (display start line register) stores the

address of the display start line. The re-mapping operation can be started at the address of the display

start line according to the internal register. Table 4 on Page 12 shows the case in which the display start

line register is set to 38h.

For those GDDRAM out of the display common range, they can be accessed for either the preparation of

vertical scrolling data or the system usage.

11

SSD0817 Series

Rev 1.0

03/2002

SOLOMON

Share Link: