3D7701-0.75 查看數據表（PDF） - Data Delay Devices

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3D7701-0.75

MONOLITHIC GATED DELAY LINE OSCILLATOR

Data Delay Devices 

3D7701

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7701 delay line oscillator architecture is

shown in Figure 1. The internal delay line is

composed of a number of delay cells connected

in series and is compensated for thermal and

supply voltage variations. A low-going edge on

the EN input starts the oscillator, with the O2

output responding immediately. The O1 output is

delayed by ½ cycle. The response of the output

when the oscillator is disabled depends on the

status of O2 when the EN signal goes high, as

shown in Figure 2. If O2 is low, it will remain low,

and the final pulse on O1 will be ½ of the period.

If O2 is high, it will go low as soon as EN goes

high, and the final pulse on both outputs will have

a width smaller than ½ the period.

Temp & Vdd

VDD

Compensation

O1

GND

Delay Line

O2

EN

Figure 1: 3D7701 Functional Diagram

EN

5ns typ

O2

O1

EN

5ns typ

O2

O1

5ns typ

Figure 2: 3D7701 Timing Diagrams

Doc #06023

DATA DELAY DEVICES, INC.

2

12/5/2006

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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