DSP56F807 查看數據表（PDF） - Motorola => Freescale

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DSP56F807

56F807 16-bit Hybrid Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

56F807 Description

• Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D

with four pins

• CAN 2.0 B Module with 2-pin port for transmit and receive

• Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

• Computer-Operating Properly (COP) Watchdog timer

• Two dedicated external interrupt pins

• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

• External reset input pin for hardware reset

• External reset output pin for system reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller

core clock

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

• Uses a single 3.3V power supply

• On-chip regulators for digital and analog circuitry to lower cost and reduce noise

• Wait and Stop modes available

1.2 56F807 Description

The 56F807 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip,

the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals

to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact

program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals that

are especially useful for applications such as motion control, smart appliances, steppers, encoders,

tachometers, limit switches, power supply and control, automotive control, engine management, noise

suppression, remote utility metering, industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The

instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F807 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external

dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each

programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It

also supports program execution from external memory.

56F807 Technical Data

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For More Information On This Product,

Go to: www.freescale.com

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