74LVC74AD(2020) 查看數據表（PDF） - NXP Semiconductors.

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74LVC74AD
(Rev.:2020)

Dual D-type flip-flop with set and reset; positive-edge trigger

NXP Semiconductors. 

Nexperia

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

10.1. Waveforms and test circuit

VI

nD input

VM

GND

VI

th

t su

1/fmax

th

tsu

nCP input

GND

VOH

VM

tW

tPHL

t PLH

nQ output

VM

VOL

VOH

Fig. 7.

nQ output

VM

VOL

tPLH

t PHL

mna422

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,

the nCP to nD hold times, and the maximum frequency

74LVC74A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 — 18 June 2020

© Nexperia B.V. 2020. All rights reserved

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