74LVTH244APW 查看數據表（PDF） - NXP Semiconductors.
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74LVTH244APW Datasheet PDF : 15 Pages
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NXP Semiconductors
74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
74LVT244A
74LVTH244A
1OE 1
1A0 2
2Y3 3
1A1 4
2Y2 5
1A2 6
2Y1 7
1A3 8
2Y0 9
GND 10
20 VCC
19 2OE
18 1Y0
17 2A3
16 1Y1
15 2A2
14 1Y2
13 2A1
12 1Y3
11 2A0
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Fig 3. Pin configuration for SO20 and (T)SSOP20
terminal 1
index area
74LVT244A
74LVTH244A
1A0 2
2Y3 3
1A1 4
2Y2 5
1A2 6
2Y1 7
1A3 8
2Y0 9
GND(1)
19 2OE
18 1Y0
17 2A3
16 1Y1
15 2A2
14 1Y2
13 2A1
12 1Y3
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Transparent top view
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4. Pin configuration for DHVQFN20
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE
1, 19
output enable input (active low)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8
data input
2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3
data output
GND
10
ground (0 V)
2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
VCC
20
supply voltage
74LVT_LVTH244A_4
Product data sheet
Rev. 04 — 3 September 2008
© NXP B.V. 2008. All rights reserved.
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