AL1402 查看數據表（PDF） - Unspecified
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AL1402 Datasheet PDF : 8 Pages
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TIMING
WDCLK
USER
OUT
LEFT CHANNEL
tDU
VALID
tDS
Figure B/Table 5 Output Delay
Symbol
Min Typ
Max Units
tDU(Master)
-10
2
27 nsec
tDU(Slave)
-7
5
30 nsec
tDS(Master)
-10
0
25 nsec
tDS(Slave)
-8
2
27 nsec
(Above specifications hold after 3900 WDCLK cycles of valid input at OPDIGIN)
one period WordClock
WDCLK
Left Just 24 23
MSB
ADAT Type II â † 19
ADAT Type I â †
MSB
15
MSB
BCLK (rising)
0
0
0
23
0
MSB
19
0
MSB
15
0
MSB
Right Just 24 ∗
23
MSB
ADAT Type II â †
19
MSB
ADAT Type I â †
15
MSB
BCLK (falling)
0
23
MSB
0
19
MSB
0
15
MSB
0
0
0
Left Just 24 23
0
23
0
MSB
MSB
Gated BCLK
Figure C.
Output
Timing
Diagram
WDCLK
SVCO
DVCO
Master Mode
12345
12345
124 125 126 127 128 129 130 131 132 133 252 253 254 255 256
124 125 126 127 128 129 130 131 132 133 252 253 254 255 256
Slave Mode
In Slave mode DVCO is not phase aligned with WDCLK and SVCO.
∗ MSB bit is sign extended to left of frame.
† These diagrams represent how data would be framed from an ADAT type I
or type II device. They are not actual modes of the AL1402. The Left
Justified Mode is recommended for ADAT formats.
Alesis Semiconductor
DS1402-0702
12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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