AM27C4096-55DC 查看數據表（PDF） - Advanced Micro Devices

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AM27C4096-55DC

512 Kilobit (64 K x 8-Bit) CMOS EPROM

Advanced Micro Devices 

TEST CONDITIONS

5.0 V

Device

Under

Test

CL

6.2 kΩ

2.7 kΩ

Note:

Diodes are IN3064 or equivalents.

Figure 3. Test Setup

08140J-7

Table 1. Test Specifications

Test Condition

All

-55

others Unit

Output Load

1 TTL gate

Output Load Capacitance, CL

(including jig capacitance)

30

100

pF

Input Rise and Fall Times

≤ 20

ns

Input Pulse Levels

0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels

1.5 0.8, 2.0 V

Output timing measurement

reference levels

1.5 0.8, 2.0 V

SWITCHING TEST WAVEFORM

3V

1.5 V

0V

Input

Test Points

1.5 V

Output

Note: For CL = 30 pF.

2.4 V

0.45 V

2.0 V

2.0 V

Test Points

0.8 V

0.8 V

Input

Output

Note: For CL = 100 pF.

08140J-8

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

Steady

OUTPUTS

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z)

KS000010-PAL

Am27C512

9

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