ASC7511D8 查看數據表（PDF） - Unspecified
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ASC7511D8 Datasheet PDF : 19 Pages
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aSC7511
35ms, allowing all SMBus devices to be reset. This follows
the SMBus 2.0 specification of 25-35ms.
When the aSC7511 detects an SMBus reset, it will prepare
to accept a new start sequence and resume
communication from a known state
1
91
9
SCL
SDA S 1 0 0 1 1 0 0 R/W A A7 A6 A5 A4 A3 A2 A1 A0 A
Start
ACK
SMBus
Device
Address
Byte
(4Ch)
from
aSC7511
ACK Stop
Register Address Byte
from By
aSC7511 Master
Figure 2. Register Address Pointer Set
1
91
91
9
SCL
SDA S 1 0 0 1 1 0 0 R/W A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
Start
ACK
SMBus
Device
Address
Byte
(4Ch)
from
aSC7511
Register Address Byte
ACK
from
aSC7511
Figure 3. Register Write
Register Data Byte
ACK Stop
from by
aSC7511 Master
Register Address
Pointer Set
(Figure 2.)
+
without stop by Master
1
91
9
S 1 0 0 1 1 0 0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 N
Re-start
ACK
SMBus
Device
Address
Byte
(4Ch)
from
aSC7511
Figure 4. Register Read
Register Data Byte
NACK Stop
from by
Master Master
1
91
9
SCL
SDA S 1 0 0 1 1 0 0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 N
Start
ACK
SMBus
Device
Address
Byte
(4Ch)
from
aSC7511
Register Data Byte
NACK Stop
from by
Master Master
Figure 5. Register Read When Read Address Already Set
1
91
9
SCL
SDA S 0 0 0 1 1 0 0 R/W A 1 0 0 1 1 0 0 1 N
Start
ACK
SMBus
Alert
Response
Address
Byte
(0Ch)
from
aSC7511
aSC7511
SMBus
Address
NACK Stop
from by
Master Master
Figure 6. SMBus Alert Response
© Andigilog, Inc. 2006
- 11 -
www.andigilog.com
August 2006 - 70A04010
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