5962-0325001VXC 查看數據表（PDF） - Atmel Corporation

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5962-0325001VXC

Rad Hard Reprogrammable FPGAs with FreeRAM

Atmel Corporation 

AT40KEL040

The Cell

Figure 5. The Cell

"1" NW NE SE SW

"1"

X

W

Figure 5 depicts the AT40KEL040 cell. Configuration bits for separate muxes and pass

gates are independent. All permutations of programmable muxes and pass gates are

legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is con-

nected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by

turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let sig-

nals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming

into the logic cell on one local bus plane can be switched onto another plane by opening

two of the pass gates. This allows bus signals to switch planes to achieve greater

routability. Up to five simultaneous local/local turns are possible.

The AT40KEL040 FPGA core cell is a highly configurable logic block based around two

3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This

means that any core cell can implement two functions of 3 inputs or one function of 4

inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated

and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every

cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an impor-

tant feature in the implementation of efficient array multipliers.

"1" N E S W

Y

Z

X

W

Y

FB

8X1 LUT

8X1 LUT

OUT

OUT

"0" "1"

"1"

V1

H1

10

Z

D CLOCK

Q RESET/SET

V2

V3

V4

V5

H2

H3

H4

H5

Pass gates

"1" OEH OEV

L

X

NW NE SE SW

4155I–AERO–06/06

Y

N ES W

X = Diagonal Direct connect or Bus

Y = Orthogonal Direct Connector Bus

W = Bus Connection

Z = Bus Connection

FB = Internal Feed back

With this functionality in each core cell, the core cell can be configured in several

“modes”. The core cell flexibility makes the AT40KEL040 architecture well suited to

most digital design application areas (see Figure 6).

9

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