AT88SC25616C-MJ(2008) 查看數據表（PDF） - Atmel Corporation

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AT88SC25616C-MJ
(Rev.:2008)

CryptoMemory 256 Kbit

Atmel Corporation 

Figure 3. Bus Timing for 2 wire communications

SCL: Serial Clock, SDA: Serial Data I/O

AT88SC25616C

Figure 4. Write Cycle Timing:

SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA

8th BIT

ACK

WORDn

Note:

STOP

CONDITION

tWR(1)

START

CONDITION

The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of

the internal clear/write cycle.

Figure 5. Data Validity

DATA

CHANGE

ALLOWED

5

5017HS–SMEM–11/08

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