ATC18RHA(2005) 查看數據表（PDF） - Atmel Corporation

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ATC18RHA
(Rev.:2005)

Rad. Hard 0.18 µm CMOS Cell-based ASIC for Space Use

Atmel Corporation 

ATC18RHA

Array Organization Though ATC18RHA is a standard cell library, pre-defined matrix sizes and pad frames have

been set so as to ease the assembly of every individual ASIC design by sticking to presently

available package cavity sizes and layouts. These are close in size to MH1RT matrix sizes.

Table 3. Standard arrays dimensions and integration capabilities

NAME

MH1 EQUIVALENCE

SIZE (mm)

ATC18RHA95_216

NA

6.19x6.19

ATC18RHA95_324

MH1099E

8.76x8.76

ATC18RHA95_404

MH1156E

10.66x10.66

ATC18RHA95_504

MH1242E

13.03x13.03

PADS (+power only)

216 (+8)

324 (+8)

404 (+8)

504 (+8)

GATES (typ)

1M

2.2M

3.5M

5.5M

Design

Management

Introduction

Atmel used to propose different design modes, where each mode indicated the designer respon-

sibilities, the design location and the design tools. With designs becoming more complex, timing

and power constraints more severe, and design behaviour more technology dependent, Atmel

believes that any design must be a close cooperation between the customer and the manufac-

turer. Therefore, only one design scenario is retained: the ASIC chip is designed by the

customer, at his site with a set of design tools supported by Atmel.

Customers now have the possibility to embark on a Multi Project Wafer (MPW). This has no

technical impact on the flow which will be described below. There will be some additional plan-

ning constraints and new milestones. This is also explained in this section.

7

4261B–AERO–06/05

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